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| NX2305 1 rev.5.0 08/19/08 typical application description the NX2305 controller ic is a combination synchronous buck and ldo controller ic designed to convert single 12v supply to low cost dual on board supply applica- tions. the synchronous controller is used for high cur- rent high efficiency step down dc to dc converter appli- cations while the ldo controller in conjunction with an external low cost n ch mosfet can be used as a very low drop out regulator in applications such as converting 3.3v to 2.5v output. internal uvlo keeps both regula- tors off until the supply voltage exceeds 9v where inde- pendent internal digital soft starts get initiated to ramp up both outputs.the switching section has hiccup cur- rent limit by sensing the rdson of synchronous mosfet. the ldo controller has feedback under voltage lock out as a short circuit protection.other features includes: 12v gate drive capability , adaptive dead band control, power good flag for the switcher controller and separate enable pins for independent power sequencing. n 12v pwm controller plus ldo controller n hiccup current limit by sensing rdson of mosfet n 12v high side and low side driver n fixed internal 300khz for switching controller n dual independent digital soft start function n adaptive deadband control n enable pin available to program the vbus uvlo n shut down switching and ldo via pulling down ensw or enldo pins n pb-free and rohs compliant ordering information features single supply 12v synchronous pwm controller with nmos ldo controller, power good & enables applications n pci graphic card on board converters n mother board on board dc to dc applications n on board single supply 12v dc to dc such as 12v to 3.3v, 2.5v or 1.8v n set top box and lcd display preliminary data sheet evaluation board available. device temperature package frequency pb-free NX2305cmtr 0 to 70 o c mlpq-16l 300khz yes NX2305cstr 0 to 70 o c soic -16l 300khz yes figure1 - typical application of NX2305 150pf c10 150uf 25mohm c8 47uf c9 n x 2 3 0 5 +12v vin1 +3.3v vin2 +1.6v/2a vout2 +3.3v vin2 r12 6.8k 1.4k r13 r10 0.75k 1.4k r11 r8 5k 5k r9 m5 1uf c12 agnd ensw enldo ldo fb ldo out 5v reg vcc 4k r1 0.1uf c1 c5 5.6nf c3 c2 1n4148 r4 8k c6 r2 3.9nf +12v vin1 +1.8v/10a vout1 r3 10k 100uf 180uf r5 10k l1 1uh 0.1uf c4 2 x 470uf c7 l2 2.2uh m2 irfr3709z m1 irfr3709z pvcc ocp pgnd bst fb comp sw hdrv ldrv 1.1k 10 r14 pgood r6 10k m3 m4 open c11 hi=sd hi=sd c13 100pf pb free product
NX2305 2 rev.5.0 08/19/08 absolute maximum ratings vcc to pgnd & bst to sw voltage .................... -0.3v to 16v bst to pgnd voltage ...................................... -0.3v to 35v sw to pgnd .................................................... -2v to 35v all other pins .................................................... -0.3v to 6.5v storage temperature range ............................... -65 o c to 150 o c operating junction temperature range ............... -40 o c to 125 o c caution: stresses above those listed in "absolute maximum ratings", may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. package information 16-lead plastic mlpq 16-lead plastic soic q?46/ o ja cw electrical specifications unless otherwise specified, these specifications apply over vcc =12v, v bst -v sw =12v, ensw=enldo=3v, and t a = 0 to 70 o c . typical values refer to t a = 25 o c . 9 10 11 12 4 3 2 1 pgnd bst ldrv pvcc en-ldo en-sw pgood fb 8 7 6 5 ldo-fb 5v reg vcc ldo-out 16 15 14 13 ocp hdrv sw comp agnd 17 1 bst ldrv gnd hdrv 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pvcc ldo-out ldo-fb vcc 5v reg en-ldo en-sw pgood fb ocp sw comp q?83/ o ja cw parameter sym test condition min typ max units reference voltage ref voltage v ref 0.8 v ref voltage line regulation 10v<=vcc<=14v 0.2 % supply voltage(vcc&v bst ) v cc voltage range v cc 8.2 14 v pv cc supply current (dynamic) i cc (dynamic) c l =3300pf 8.5 ma v bst voltage range v bst to v sw 8.2 14 v v bst supply current(static) v bst (static) ensw=low enldo=low 0.2 ma v cc supply current (static) i cc (static) ma ensw=low enldo=low 8 NX2305 3 rev.5.0 08/19/08 n parameter sym test condition min typ max units v bst supply current (dynamic) v bst (dynamic) c l =3300pf 9.2 ma under voltage lockout v cc -threshold v cc _uvlo v cc rising (note1) 6.8 v v cc hysterises v cc falling (note1) 300 mv oscillator (rt) frequency f s 300 khz ramp-amplitude voltage v ramp 1.1 v max duty cycle 94 % min duty cycle 0 % error amplifiers open loop gain 50 65 db transconductance gm 2000 umho comp sd threshold 0.2 v input bias current ib 100 na en & ss soft start time tss 6.8 ms enable hi threshold v enthh 1.24 v enable hysterises v enthl 30 mv high side driver, hdrv, bst, sw (c l =3300pf) rise time thdrv(rise) 10% to 90% 30 ns fall time thdrv(fall) 90% to 10% 20 ns low side driver , ldrv, pvcc, pgnd(c l =3300pf) output impedance, sourcing current r source (ldrv) i=200ma 2.2 ohm output impedance, sinking current r sink (ldrv) i=200ma 1 ohm rise time tldrv(rise) 10% to 90% 30 ns fall time tldrv(fall) 90% to 10% 20 ns ldo controller fb pin- bias current 1 ua high output voltage 11.1 v low output voltage 0.2 v high output source current 1.9 ma output impedance , sourcing current r source (hdrv) i=200ma tdead(l to h) deadband time ldrv going low to hdrv going high, 10% to 10% deadband time tdead(h to l) sw going low to ldrv going high, 10% to 10% 50 ns 50 ns ohm 3.6 1 ohm output impedance , sinking current r sink (hdrv) i=200ma NX2305 4 rev.5.0 08/19/08 note1: vcc is connected to ensw pin via a resistor divider. in vcc uvlo test, ensw pin is open. note2: this parameter is guaranteed by design but not tested in production(gbnt). parameter sym test condition min typ max units open loop gain gbnt(note 2) 50 db fb under voltage trip point 50 % power good(pgood) threshold voltage as % of vref fb ramping up 90 % hysteresis 5 % ocp adjust ocp current setting 40 ua NX2305 5 rev.5.0 08/19/08 pin descriptions pin symbol pin description ic?s supply voltage. this pin biases the internal logic circuits. a high freq 1uf ceramic capacitor is placed as close as possible to and connected to this pin and ground pin. the maximum rating of this pin is 16v. this pin supplies voltage to high side fet driver. a high freq 0.1uf ceramic capacitor is placed as close as possible to and connected to these pins and sw pin. a resistor divider is connected from the ldo bus voltage to this pin that holds off the ldo soft start until this threshold is reached. an external low cost mosfet can be connected to this pin for external enable control. a resistor divider is connected from the respective switcher bus voltage to this pin that holds off the controller's soft start until this threshold is reached. an external low cost mosfet can be connected to this pin for external enable control. this pin is the error amplifier inverting input. this pin is connected via resistor divider to the output of the switching regulator to set the output dc voltage. this pin is the output of error amplifier and is used to compensate the voltage control feedback loop. this pin is connected to the drain of the external low side mosfet and is the input of the over current protection(ocp) comparator. an internal current source 40ua is flown to the external resistor which sets the ocp voltage across the rdson of the low side mosfet. current limit point is this voltage divided by the rds-on. once this threshold is reached the hdrv and ldrv pins are switched low and an internal hiccup circuit is set that recycles the soft start circuit after 2048 switching cycles. this pin is connected to source of high side fet and provides return path for the high side driver. it is also used to hold the low side driver low until this pin is brought low by the action of high side turning off. ldrv can only go high if sw is below 1v threshold . high side gate driver output. low side gate driver output. supply voltage for the low side fet driver. a high frequency 1uf ceramic cap must be connected from this pin to the pgnd pin as close as possible. ldo controller feedback input. this pin is connected via resistor divider to the output of the switching regulator to set the output dc voltage.if the ldofb pin is pulled below 0.4v, an internal comparator after a delay pulls down ldoout pin and initiates the hiccup circuitry. during the startup this latch is not activated, allowing the ldofb pin to come up and follow the soft started vref voltage. ldo controller output. this pin is controlling the gate of an external nch mosfet. the maximum rating of this pin is 16v. output of an internal 5v regulator. vcc bst enldo ensw fb comp ocp sw hdrv ldrv pvcc ldo_fb ldo_out 5v reg NX2305 6 rev.5.0 08/19/08 an open drain output that requires a pull up resistor to vcc or a voltage lower than vcc. when fb pin reaches 90% of the reference voltage pgood transitions from lo to hi state. power ground pin for low side driver. in soic16 package, pgnd and agnd are combined together called gnd. analog ground. in mlpd16 package, pad is agnd. pin symbol pin description pgood pgnd agnd a(( NX2305 7 rev.5.0 08/19/08 bias generator 1.25v 0.8v 5vreg bst hdrv sw pvcc ldrv fb comp osc r s q digital start up uvlo por v ensw gnd control logic ocp comparator pgnd ocp vcc ramp enldo 1.25/1.15 ldo digital start up ldoout fbldo por 0.4 bias regulator 0.2v comp oc start start hiccup logic oc 1.3v clamp 0.6v clamp start pgood fb 0.9vref /0.85vref pwm 0.8v ensw_hi ensw_hi 40ua enthh ocp i v enthl 20k 90k block diagram figure 2 - simplified block diagram of the NX2305 NX2305 8 rev.5.0 08/19/08 application information symbol used in application information: v in - input voltage v out - output voltage i out - output current d v ripple - output voltage ripple f s - switching frequency d i ripple - inductor current ripple design example power stage design requirements: v in =12v v out =1.8v i out =10a d v ripple <=20mv d v tran <=100mv @ 10a step f s =300khz output inductor selection the selection of inductor value is based on induc- tor ripple current, power rating, working frequency and efficiency. larger inductor value normally means smaller ripple current. however if the inductance is chosen too large, it brings slow response and lower efficiency. usu- ally the ripple current ranges from 20% to 40% of the output current. this is a design freedom which can be decided by design engineer according to various appli- cation requirements. the inductor value can be calcu- lated by using the following equations: inout out out rippleins rippleoutput v-vv 1 l= ivf i=ki ...(1) where k is between 0.2 to 0.4. select k=0.3, then out out 12v-1.8v1.8v1 l= 0.310a12v300khz l=1.7uh choose l out =2.2uh, then coilcraft inductor do5010p-222hc is a good choice. current ripple is calculated as = inout out ripple outins v-vv 1 i= lvf 12v-1.8v1.8v1 =2.3a 2.2uh12v300khz ...(2) output capacitor selection output capacitor is basically decided by the amount of the output voltage ripple allowed during steady state(dc) load condition as well as specification for the load transient. the optimum design may require a couple of iterations to satisfy both condition. based on dc load condition the amount of voltage ripple during the dc load condition is determined by equation(3). d d=d+ ripple rippleripple sout i vesri 8fc ...(3) where esr is the output capacitors' equivalent series resistance,c out is the value of output capacitors. typically when large value capacitors are selected such as aluminum electrolytic,poscap and oscon types are used, the amount of the output voltage ripple is dominated by the first term in equation(3) and the second term can be neglected. for this example, poscap are chosen as output capacitors, the esr and inductor current typically de- termines the output voltage ripple. d ==w d ripple desire ripple v 20mv esr=8.7m i2.3a ...(4) if low esr is required, for most applications, mul- tiple capacitors in parallel are better than a big capaci- tor. for example, for 20mv output ripple, poscap 2r5tpe470m9 with 9m w are chosen. eripple ripple esri n v d = d . ..(5) number of capacitor is calculated as w = 9m2.3a n 20mv n =1.03 the number of capacitor has to be round up to a integer. choose n =2. NX2305 9 rev.5.0 08/19/08 if ceramic capacitors are chosen as output ca- pacitors, both terms in equation (3) need to be evalu- ated to determine the overall ripple. usually when this type of capacitors are selected, the amount of capaci- tance per single unit is not sufficient to meet the tran- sient specification, which results in parallel configura- tion of multiple capacitors. for example, one 100uf, x5r ceramic capacitor with 2m w esr is used . the amount of output ripple is d=w+ =+= ripple 2.3a v2m2.3a 8300khz100uf 4.6mv9.6mv14.2mv although this meets dc ripple spec, however it needs to be studied for transient requirement. based on transient requirement typically, the output voltage droop during transient is specified as d v droop d v tran < @step load d i step during the transient, the voltage droop during the transient is composed of two sections. one section is dependent on the esr of capacitor, the other section is a function of the inductor, output capacitance as well as input, output voltage. for example, for the over- shoot when load from high load to light load with a d i step transient load, if assuming the bandwidth of system is high enough, the overshoot can be esti- mated as the following equation. 2 out overshootstep out v vesri 2lc d=d+t ...(6) where t is the a function of capacitor,etc. crit step outcrit out 0ifll li esrcifll v ? d t= -3 ? ? ...(7) where outouteeout crit stepstep esrcvesrcv l ii == dd ...(8) where esr e and c e represents esr and capaci- tance of each capacitor if multiple capacitors are used in parallel. the above equation shows that if the selected out- put inductor is smaller than the critical inductance, the voltage droop or overshoot is only dependent on the esr of output capacitor. for low frequency capacitor such as electrolytic capacitor, the product of esr and ca- pacitance is high and crit ll is true. in that case, the transient spec is mostly like to dependent on the esr of capacitor. most case, the output capacitor is multiple capaci- tor in parallel. the number of capacitor can be calcu- lated by the following estep 2 out tranetran esri v n v2lcv d =+t dd ...(9) where crit step eecrit out 0ifll li esrcifll v ? d t= -3 ? ? ...(10) for example, assume voltage droop during tran- sient is 100mv for 10a load step. if the poscap 2r5tpe470m9 (470uf, 9mohm esr) is used, the crticial inductance is given as eeout crit step esrcv l i 9m470f1.8v 0.76h 10a == d wm =m the selected inductor is 2.2uh which is bigger than critical inductance. in that case, the output voltage tran- sient not only dependent on the esr, but also capaci- tance. number of capacitor is step ee out li esrc v 2.2h10a 9m470f7.97us 1.8v d t=- m =-wm= estep 2 out tranetran 2 esri v n v2lcv 9m10a1.8v (7.97us) 100mv22.2h470f100mv 1.44 d =+t dd w =+ mm = NX2305 10 rev.5.0 08/19/08 the number of capacitors has to satisfied both ripple and transient requirement. overall, we choose n=2. it should be considered that the proposed equa- tion is based on ideal case, in reality, the droop or over- shoot is typically more than the calculation. the equa- tion gives a good start. for more margin, more capaci- tors have to be chosen after the test. typically, for high frequency capacitor such as high quality poscap es- pecially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the esr of capacitors is so low that the pcb parasitic can affect the results tremendously. more capacitors have to be selected to compensate these parasitic parameters. compensator design due to the double pole generated by lc filter of the power stage, the power system has 180 o phase shift , and therefore, is unstable by itself. in order to achieve accurate output voltage and fast transient response, compensator is employed to provide highest possible bandwidth and enough phase margin. ideally, the bode plot of the closed loop system has crossover frequency between 1/10 and 1/5 of the switching frequency, phase margin greater than 50 o and the gain crossing 0db with - 20db/decade. power stage output capacitors usually decide the compensator type. if electrolytic capacitors are chosen as output capacitors, type ii compensator can be used to compensate the system, because the zero caused by output capacitor esr is lower than cross- over frequency. otherwise type iii compensator should be chosen. a. type iii compensator design for low esr output capacitors, typically such as sanyo oscap and poscap, the frequency of esr zero caused by output capacitors is higher than the cross- over frequency. in this case, it is necessary to compen- sate the system with type iii compensator. the follow- ing figures and equations show how to realize the type iii compensator by transconductance amplifier. z1 42 z2 233 p1 33 p2 12 4 12 1 f ...(11) 2rc 1 f ...(12) 2(rr)c 1 f ...(13) 2rc 1 f ...(14) cc 2r cc = p = p+ = p = p + where f z1 ,f z2 ,f p1 and f p2 are poles and zeros in the compensator. the transfer function of type iii compensator for transconductance amplifier is given by: e mf out minin1 v 1gz v1gzz/r - = ++ for the voltage amplifier, the transfer function of compensator is e f out in v z vz - = to achieve the same effect as voltage amplifier, the compensator of transconductance amplifier must satisfy this condition: r4>>2/gm. and it would be desir- able if r1||r2||r3>>1/gm can be met at the same time. zin zf vout vref fb r2 r1 r3 r4 c3 c1 c2 ve gm figure 3 - type iii compensator using transconductance amplifier NX2305 11 rev.5.0 08/19/08 case 1: f lc NX2305 14 rev.5.0 08/19/08 case 2: type ii compensator can also be realized by simple rc circuit without feedback as shown in figure 9. r3 and c1 introduce a zero to cancel the double pole effect. c2 introduces a pole to suppress the switching noise. the following equations show the compensator pole zero lo- cation and constant gain. 1 m3 12 z 31 p 32 r gain=gr ... (18) r+r 1 f= ... (19) 2rc 1 f ... (20) 2rc p ? p gain(db) compensator loop gain power stage 40db/decade 20db/decade gain f z lc f esr f o f f p figure 8 - bode plot of type ii compensator gm r3 c1 c2 ve vout vref fb r2 r1 figure 9 - type ii compensator with transconductance amplifier for this type of compensator, f o has to satisfy f lc NX2305 16 rev.5.0 08/19/08 where q hgate is the high side mosfets gate charge,q lgate is the low side mosfets gate charge,v hgs is the high side gate source voltage, and v lgs is the low side gate source voltage. this power dissipation should not exceed maxi- mum power dissipation of the driver device. soft start and enable NX2305 has digital soft start for switching control- ler and has one enable pin for this start up. when the power ready (por) signal is high and the voltage at enable pin is above v enthh, the internal digital counter starts to operate and the voltage at positive input of error amplifier starts to increase, the feedback network will force the output voltage follows the reference and starts the output slowly. after 2048 cycles, the soft start is complete and the output voltage is regulated to the de- sired voltage decided by the feedback resistor divider. por digital start up v + vbus r1 r2 ensw or enldo 10k on off enthh v enthl figure 11 - enable and shut down the NX2305 with enable pin. the start up of NX2305 can be programmed through resistor divider at enable pin. for example, if the input bus voltage is 12v and we want NX2305 starts when vbus is above 8v. we can select - = enthh2 1 enthh (8vv)r r v the NX2305 can be turned off by pulling down the enable pin by extra signal mosfet as shown in the above figure. when enable pin is below v enthl, the digi- tal soft start is reset to zero. in addition, all the high side and low side driver is off and no negative spike will be generated during the turn off. one sanyo os-con 16svp180m 16v 180uf 20m w with 3.64a rms rating are chosen as input bulk capacitors. power mosfets selection the NX2305 requires two n-channel power mosfets. the selection of mosfets is based on maximum drain source voltage, gate source voltage, maximum current rating, mosfet on resistance and power dissipation. the main consideration is the power loss contribution of mosfets to the overall converter efficiency. in this design example, two irfr3709z are used. they have the following parameters: v ds =30v,r dson =6.5m w ,q gate =17nc. there are two factors causing the mosfet power loss:conduction loss, switching loss. conduction loss is simply defined as: 2 hconoutds(on) 2 lconoutds(on) totalhconlcon p=idr p=i(1d)rk p=pp - + k ...(23) where the r ds(on) will increases as mosfet junc- tion temperature increases, k is r ds(on) temperature dependency. as a result, r ds(on) should be selected for the worst case, in which k approximately equals to 1.4 at 125 o c according to irfr3709z datasheet . conduc- tion loss should not exceed package rating or overall system thermal budget. switching loss is mainly caused by crossover conduction at the switching transition. the total switching loss can be approximated. swinoutsws 1 pvitf 2 = . ..(24) where i out is output current, t sw is the sum of t r and t f which can be found in mosfet datasheet, and f s is switching frequency. switching loss p sw is frequency dependent. also mosfet gate driver loss should be consid- ered when choosing the proper power mosfet. mosfet gate driver loss is the loss generated by dis- charg i ng the gate capacitor and is dissipated in driver circuits.it is proportional to frequency and is defined as: gatehgatehgslgatelgss p(qvqv)f =+ ...(25) NX2305 17 rev.5.0 08/19/08 over current protection over current protection for NX2305 is achieved by sensing current through the low side mosfet. an inter- nal current source of 40ua flows through an external re- sistor connected from ocp pin to sw node sets the over current protection threshold. when synchronous fet is on, the voltage at node sw is given as swldson v=-ir the voltage at pin ocp is given as ocpocpsw ir+v when the voltage is below zero, the over current occurss as shown in figure 12. ocp comparator ocp 40ua ocp i ocp r sw figure 12 - over current protection vbus the over current limit can be set by the following equation = setocpocpdson iir/r if the mosfet r dson =9m w , and the current limit is set at 15a, then w ===w setdson ocp ocp ir 15a9m r3.375k i40ua choose r ocp =4k w ldo selection guide NX2305 offers a ldo controller. the selection of mosfet to meet ldo is more straight forward. the selection is that the rdson of mosfet should meet the dropout requirement. for example. v ldoin =3.3v v ldoout =2.5v i load =2a the maximum rdson of mosfet should be rdsonldoinldooutload r(vv)i (3.3v2.5v)/2a0.4 =- =-=w most of mosfets can meet the requirement. more important is that mosfet has to be selected right pack- age to handle the thermal capability. for ldo, maxi- mum power dissipation is given as lossldoinldooutload p(vv)i (3.3v2.5v)2a1.6w =- =-= select ir mosfet irfr3706 with 9m w r dson is sufficient. ldo compensation the diagram of ldo controller including vcc regu- lator is shown in figure 13. r r rc cc + ldo input rload esr co vref f1 f2 figure 13 - NX2305 ldo controller. for most low frequency capacitor such as electro- lytic, poscap, oscon, etc, the compensation param- eter can be calculated as follows. m c of1m gesr 1 c= 4fr1+gesr p where f o is the desired crossover frequency. typically, in this ldo compensation, crossover frequency f o has to be higher than zero caused by esr. f o is typically around several tens khz to a few hundred khz. for this example, we select fo=100khz. g m is the forward trans-conductance of mosfet. for irfr3706, g m =53. select r f1 =5kohm. output capacitor is sanyo poscap 4tpe150mi with 150uf, esr=18mohm. NX2305 18 rev.5.0 08/19/08 c 15318m c= =77pf 4100khz5k1+5318m w pww choose c c =82pf. for electrolytic or poscap, r c is typically selected to be zero. r f2 is determined by the desired output voltage. f1ref f2 ldooutref rv r= vv 5k0.8v = 1.6v0.8v =5k - w - w choose r f2 =5k w. when ceramic capacitors or some low esr bulk capacitors are chosen as ldo output capacitors, the zero caused by output capacitor esr is so high that crossover frequency f o has to be chosen much higher than zero caused by r c and c c and much lower than zero caused by esr . for example, 10uf ceramic is used as output capacitor. we select fo=100khz, r f1 =5kohm and select mosfet mtd3055(g m =5). r c and c c can be calculated as follows. oo cf1 m 2fc r=r 0.5g 2100khz10uf =5k 0.55s =12.56k p p w w choose r c =12.7k w. o c cm 10c c= rg 1010uf = 12.7k5s =1.6nf w choose c c =1.5nf. current limit for ldo current limit of ldo is achieved by sensing the ldo feedback voltage. when ldo_fb pin is below 0.4v, the ic goes into hiccup mode. the ic will turn off all the channel for 2048 cycles and start to restart system again. layout considerations the layout is very important when designing high frequency switching converters. layout will affect noise pickup and can cause a good design to perform with less than expected results. there are two sets of components considered in the layout which are power components and small sig- nal components. power components usually consist of input capacitors, high-side mosfet, low-side mosfet, inductor and output capacitors. a noisy environment is generated by the power components due to the switch- ing power. small signal components are connected to sensitive pins or nodes. a multilayer layout which in- cludes power plane, ground plane and signal plane is recommended . layout guidelines: 1. first put all the power components in the top layer connected by wide, copper filled areas. the input capacitor, inductor, output capacitor and the mosfets should be close to each other as possible. this helps to reduce the emi radiated by the power loop due to the high switching currents through them. 2. low esr capacitor which can handle input rms ripple current and a high frequency decoupling ceramic cap which usually is 1uf need to be practically touch- ing the drain pin of the upper mosfet, a plane connec- tion is a must. 3. the output capacitors should be placed as close as to the load as possible and plane connection is re- quired. 4. drain of the low-side mosfet and source of the high-side mosfet need to be connected thru a plane ans as close as possible. a snubber nedds to be placed as close to this junction as possible. 5. source of the lower mosfet needs to be con- nected to the gnd plane with multiple vias. one is not enough. this is very important. the same applies to the output capacitors and input capacitors. 6. hdrv and ldrv pins should be as close to mosfet gate as possible. the gate traces should be NX2305 19 rev.5.0 08/19/08 150pf c10 150uf 25mohm c8 47uf c9 n x 2 3 0 5 +12v vin1 +1.2v/2a vout2 +1.8v vout1 r12 6.8k 1.4k r13 r10 0.75k 1.4k r11 r8 5k 5k r9 0 r7 m5 1uf c12 agnd ensw enldo ldo fb ldo out 5v reg vcc 5k r1 1uf c1 c5 1.8nf c3 c2 1n4148 r4 40.2k c6 r2 820pf +12v vin1 +1.8v/10a vout1 r3 49.9k 100uf 180uf r5 40.2k l1 1uh 0.1uf c4 1500uf 13mohm c7 l2 2.2uh m2 ir3711 m1 ir3709 pvcc ocp pgnd bst fb comp sw hdrv ldrv 22.1k 10 r14 pgood r6 10k m3 m4 open c11 hi=sd hi=sd c13 27pf +1.8v vout1 figure 14 - typical application of NX2305 with single power supply wide and short. a place for gate drive resistors is needed to fine tune noise if needed. 7. vcc capacitor, bst capacitor or any other by- passing capacitor needs to be placed first around the ic and as close as possible. the capacitor on comp to gnd or comp back to fb needs to be place as close to the pin as well as resistor divider. 8. the output sense line which is sensing output back to the resistor divider should not go through high frequency signals. 9. all gnds need to go directly thru via to gnd plane. 10. the feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the ic. 11. in multilayer pcb, separate power ground and analog ground. these two grounds must be connected together on the pc board layout at a single point. the goal is to localize the high current path to a separate loop that does not interfere with the more sensitive ana- log control function. |
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